International Journal of Applied Control, Electrical and Electronics Engineering (IJACEEE)

 Paper Title : A Ultra Low Power Router Design for Network on Chip

Author's Details :
Alaaudeen K.M, Vengatesh Kumar S, Department of Electronics & Communication Engineering, Mohammed Sathak Engineering College, Ramnad, TN, India

ABSTRACT

The design of more complex systems becomes an increasingly difficult task because of different issues related to latency, design reuse, throughput and cost that has to be considered while designing. In Real-time applications there are different communication needs among the cores. When NoCs (Networks
on chip) are the means to interconnect the cores, use of some techniques to optimize the communication are indispensable. From the performance point of view, large buffer sizes ensure performance during different applications execution. But unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case latency incurs in extra dissipation for the mean case, which is much more frequent. Reconfigurable router
architecture for NOC is designed for processing elements communicate over a second communication level using direct-links between another node elements. Several possibilities to use the
router as additional resources to enhance complexity of modules are presented. The reconfigurable router is evaluated in terms of area, speed and latencies. The proposed router was described in VHDL and used the ModelSim tool to simulate the code. Analyses the average power consumption, area, and frequency results to a standard cell library using the Design Compiler tool. With the reconfigurable router it was possible to reduce the congestion in the network, while at the same time reducing power dissipation and improving energy.

KEYWORDS
Buffer, Latency, Network on chip, reconfigurable router, Throughput

https://airccse.com/ijaceee/papers/6118ijaceee02.pdf