ON VERTICAL INTEGRATION FRAMEWORK ELEMENT OF TRANSISTOR-TRANSISTOR LOGIC E.L. Pankratov1 , E.A. Bulaeva1, 2 1 Nizhny Novgorod State University, 23 Gagarin avenue, Nizhny Novgorod, 603950, Russia 2 Nizhny Novgorod State University of Architecture and Civil Engineering, 65 Il'insky street, Nizhny Novgorod, 603950, Russia ABSTRACT In this paper we introduce an approach to increase vertical integration of elements of transistor-transistor logic with function AND-NOT. Framework the approach we consider a heterostructure with special configuration. Several specific areas of the heterostructure should be doped by diffusion or ion implantation. Annealing of dopant and/or radiation defects should be optimized. KEYWORDS Transistor-transistor logic; optimization of manufacturing; decreasing of dimensions of transistor; analytical approach for modelling Original Source URL : https://airccse.com/ijaceee/papers/3315ijaceee...
