PRODESIGN OF HIGH PERFORMANCE NOC ROUTER
PRODESIGN OF HIGH PERFORMANCE NOC
ROUTER
Mitun S.
PG Scholar, Electronics & Communication Dept.
Hindusthan Institute of Technology, Coimbatore.
ABSTRACT
This is a high performance NoC Router that handles precise localizations of the faulty parts of the NoC. The
proposed router is based on new error detection mechanisms suitable for dynamic NoCs, where the position of
processor elements or faulty blocks varies during runtime. Indeed, I propose an online Error detection
mechanism using CRC Algorithm. Proposed mechanism is able to discriminate permanent and transient errors
and localize precisely the position of the faulty blocks in the NoC routers, while preserving the throughput, the
network load, and the data packet latency.
KEYWORDS
Network on Chip, Loop Back Module, Error Detection Code, CRC Algorithm.
Original Source URL : http://airccse.com/ijaceee/papers/2114ijaceee03.pdf
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