A ULTRA-LOW POWER ROUTER DESIGN FOR NETWORK ON CHIP
Alaaudeen K.M, Vengatesh Kumar S Department of Electronics & Communication Engineering, Mohammed Sathak Engineering College, Ramnad, TN, India ABSTRACT The design of more complex systems becomes an increasingly difficult task because of different issues related to latency, design reuse, throughput and cost that has to be considered while designing. In Real-time applications there are different communication needs among the cores. When NoCs (Networks on chip) are the means to interconnect the cores, use of some techniques to optimize the communication are indispensable. From the performance point of view, large buffer sizes ensure performance during different applications execution. But unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case latency incurs in extra dissipation for the mean case, which is much more frequent. Reconfigurable router architecture for NOC i...
